The invention relates in general to a method of forming deep trench capacitors. In particular, the invention relates to a method of forming deep trench capacitors using self-starved atomic layer chemical vapor deposition (self-starved ALCVD).
DRAM is readable and writeable memory. Each DRAM cell consists of one transistor and one capacitor, obtaining high integrity compared with other memory types, allowing comprehensive application in computers and electronic products. Currently, plane transistors with deep trench capacitors are designed to have a 3-dimensional capacitor structure formed in the deep trench of the semiconductor substrate, minimizing dimensions and power consumption, and accelerating operating speed.
FIG. 1A is a plane view of the deep trench in a conventional DRAM cell. In a folded bit line structure, each active area includes two word lines (WL1 & WL2) and one bit line (BL), with CB representing a bit line contact, and DT representing a deep trench.
FIG. 1B is a cross section of a deep trench capacitor in a conventional DRAM cell. A semiconductor silicon substrate 10 has a deep trench DT, the lower area of which acts as deep trench capacitor 12, consisting of a buried plate, a node dielectric, and a storage node. In fabrication of the deep trench capacitor 12, a deep trench DT is formed in the p-type semiconductor substrate 10 using reactive ion etch (RIE), and n+-type ions are diffused into the lower area of the deep trench DT using a heavy doping oxide, such as ASG, with high temperature annealing, so that an n+-type diffusion area 14 is formed to act as the buried plate of the deep trench capacitor 12. A silicon nitride/oxide structure 16 is formed at the inner sidewall and bottom of the lower area of the deep trench DT, acting as the node dielectric of the deep trench capacitor 12. Subsequently, an n+-type doped first polysilicon layer 18 is formed inside the deep trench DT, recessing the first polysilicon layer 18 at a predetermined depth to act as the storage node of the deep trench capacitor 12.
After completing of the above deep trench capacitor 12, a collar dielectric 20 is fabricated on the upper sidewalls of the deep trench DT. An n+-type doped second polysilicon layer 22 and a third polysilicon layer 24 are sequentially formed on the upper deep trench DT. Afterward, a shallow trench isolation (STI) structure 26, word lines (WL1 & WL2), source/drain diffusion area 28, bit line contacts (CB), and bit lines (BL) processes are performed. The STI structure 26 is formed to isolate the adjacent DRAM cells.
In order to connect the deep trench capacitor 12 to the transistor located on the surface of the substrate 10, a buried strap outdiffusion area 30 is formed in the silicon substrate 10 near the top side area of the deep trench DT, acting as a node junction. The buried strap out-diffusion area 30 is formed using n+-type ions from the second polysilicon layer 22 through the third polysilicon layer 24, and diffused to the adjacent silicon substrate 10, so that the third polysilicon layer 24 acts as a buried strap 24. The collar dielectric layer 20 is formed to insulate the buried strap out-diffusion area 30 and the buried plate 14, potentially preventing from sidewalls current leakage.
FIGS. 2A˜2E are cross sections showing fabrication of the conventional deep trench capacitor, wherein the polysilicon conductive layer is filled first, and the collar dielectric is then formed. In FIG. 2A, a p-type semiconductor substrate comprises a pad layer 32, a deep trench DT, an n+-type diffusion area 14, a silicon nitride/oxide layer structure (NO structure) 16, and an n+-type doped first polysilicon layer 18. Next, in FIG. 2B, the first polysilicon layer 18 is recessed and the NO structure 16 at the upper of the deep trench DT is removed. In FIG. 2C, a silicon oxide layer 36 is formed on the pad structure 32 and the deep trench DT using CVD, and the portion of the silicon oxide layer 36 on the top of the first polysilicon layer 18 is then anisotropically etched.
Subsequently, in FIG. 2D, an n+-type doped second polysilicon layer 22 is filled into the deep trench DT, and recessed to a predetermined depth. Finally, in FIG. 2E, a portion of the silicon oxide layer 36 is removed using wet etching resulting in the protrusion of the second polysilicon layer 22. The remained silicon oxide layer 36 acts as a collar dielectric.
In the conventional process, two steps of filling and recessing the polysilicon layers are needed before forming the buried strap 24. While conventional process of fabrication the deep trench capacitor is too long and complicate, process reduction is required.